D/a converter circuit

ABSTRACT

A D/A converter circuit that converts a digital signal to an analog signal within a short period of time. The A/D converter circuit has a plurality of resistors, which are connected in series between a high potential power supply and a low potential power supply, a first switch group, and a second switch group. The first switch group is formed by switches, which are connected to nodes between the resistors. The second switch group is formed by switches, which are also connected to the nodes. A decoder circuit is connected to the switch groups to selectively close one of the first switches and one of the second switches.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a D/A converter circuit, andmore particularly, to a D/A converter circuit provided with resistorsthat divide the potential difference between a high potential powersupply and a low potential power supply to generate divided voltages.

[0002] A D/A converter circuit is a circuit for converting a digitalsignal to an analog signal. The D/A converter circuit may also be usedas an internal circuit of an analog-to-digital converter circuit (A/Dconverter circuit), which converts an analog signal to a digital signal.

[0003]FIG. 1 is a schematic circuit diagram of a prior art string-typeD/A converter circuit 31. The D/A converter circuit 31 includes avoltage dividing circuit 32. The voltage dividing circuit 32 includes aplurality (e.g., six) of resistors R31, R32, R33, R34, R35, R36connected in series between a high potential power supply VD and a lowerpotential power supply GND. The resistors R31-R36 have the sameresistance. Further, the resistors R31-R36 equally divide the potentialdifference between the high potential power supply VD and the lowpotential power supply GND to generate divided voltages at nodes N31,N32, N33, N34, N35 between the resistors R31-R36.

[0004] Each of the nodes N31-N35 (nodes connected to the high potentialpower supply VD and the low potential power supply GND may also beincluded) is connected to the same output terminal by a switch. FIG. 1shows only switches SW31, SW32 respectively connected to nodes N31, N32.A decoder circuit (not shown) generates an output formed from a digitalsignal, which has a plurality of bits, to control the activation andinactivation of each switch.

[0005] Accordingly, the D/A converter circuit 31 outputs an analogsignal OUT3 having a divided voltage that is applied at the node that isassociated with the switch activated by the digital signal of thedecoder circuit. A first capacitor C3, which is shown in FIG. 1,includes the capacitance of each switch and the capacitance of asucceeding stage circuit (not shown), which is connected to the outputterminal of the D/A converter circuit 31.

[0006] The D/A converter circuit 31 requires a relatively long period oftime from when the activation and inactivation of the switches SW31,SW32 is switched to when the set voltage at node N36 is generated.

[0007] When the digital signal activates the switch SW31 to output theanalog signal OUT3 at a divided voltage of 5/6×VD, and then the switchSW31 is inactivated and the switch SW32 is activated, the dividedvoltage at node N32 is lower than that at node N31. The discharging ofthe capacitor C3 decreases the voltage at node N36. This causes thevoltage at node N36 to be substantially the same as that at node N32.

[0008] On the other hand, when the digital signal activates the switchSW32 to output the analog signal OUT3 at a divided voltage of 4/6×VD,and then the switch SW32 is inactivated and the switch SW31 isactivated, the divided voltage at node N31 is higher than that at nodeN32. The charging of the capacitor C3 increases the voltage at node N36.This causes the voltage at N36 to be substantially the same as that atnode N31.

[0009] The converting period of the D/A converter circuit 31 (i.e., thetime required for the voltage at node N36 to stabilize) is determined bythe charging/discharging time of the capacitor C3. The resistance of theresistors R31-R36 relative to the capacitance C3 and the ON resistanceof each switch determine the charging/discharging time of the capacitorC3.

[0010] The resistance of the resistors R31-R36 and the ON resistance ofthe switches SW31, SW32 may be decreased to reduce the discharging orcharging time of the capacitor C3 and shorten the converting time.However, a decrease in the resistance of the resistors R31-R36 increasesthe current consumption between the high potential power supply VD andthe low potential power supply GND. Further, a decrease in the ONresistance of each switch increases the size of the switch, whichincreases the capacitance component of the switch. As a result, thecapacitance of the capacitor C3 increases and hinders reduction of theconverting time.

SUMMARY OF THE INVENTION

[0011] The object of the present invention is to provide a D/A convertercircuit that reduces the time for converting a digital signal to ananalog signal.

[0012] To achieve the above object, the present invention provides a D/Aconverter circuit including a plurality of impedance elements connectedin series between a first power supply and a second power supply and aplurality of switch groups including a first switch group and a secondswitch group. The first switch group is formed by a plurality of firstswitches connected to at least a plurality of nodes between theplurality of impedance elements, and the second switch group is formedby a plurality of second switches connected to at least the plurality ofnodes. A control circuit is connected to the switch groups forselectively closing one of the first switches and one of the secondswitches.

[0013] A further perspective of the present invention is a D/A convertercircuit including a plurality of resistors connected in series between afirst power supply and a second power supply. The plurality of resistorsinclude a first resistor adjacent to the first power supply and a secondresistor adjacent to the second power supply. A first switch group isformed by a plurality of first switches connected to a plurality ofinter-resistor nodes between the resistors and to a first inter-powersource node between the first power supply and the first resistor. Asecond switch group is formed by a plurality of second switchesconnected to the inter-resistor nodes and to a second inter-power sourcenode between the second power source and the second resistor. A decodercircuit is connected to the first and second switch groups toselectively close one of the first switches and one of the secondswitches.

[0014] Other aspects and advantages of the present invention will becomeapparent from the following description, taken in conjunction with theaccompanying drawings, illustrating by way of example the principles ofthe invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The invention, together with objects and advantages thereof, maybest be understood by reference to the following description of thepresently preferred embodiments together with the accompanying drawingsin which:

[0016]FIG. 1 is a schematic circuit diagram showing a prior art D/Aconverter circuit;

[0017]FIG. 2 is a schematic circuit diagram of a D/A converter circuitaccording to a preferred embodiment of the present invention;

[0018]FIG. 3 is a table illustrating the control logic of the D/Aconverter circuit of FIG. 2;

[0019]FIG. 4 is a schematic diagram illustrating the principle of thepresent invention; and

[0020] FIGS. 5(a) and 5(b) are diagrams respectively showing thewaveform of an output voltage of a voltage dividing circuit and aninternal node voltage of the voltage dividing circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] A D/A converter circuit 11 according to a preferred embodiment ofthe present invention will now be described with reference to FIGS. 2 to5. The D/A converter circuit 11 includes a voltage dividing circuit 12.The voltage dividing circuit 12 is connected between a high potentialpower supply VD, which serves as a first power supply, and a lowpotential power supply GND (in the preferred embodiment, the groundGND), which serves as a second power supply.

[0022] The voltage dividing circuit 12 includes a plurality (e.g.,eight) of resistors R1-R8, a first switch group 13, and a second switchgroup 14. The resistors R1-R8 serve as impedance elements and areconnected in series between the high potential power supply VD and thelow potential power supply GND.

[0023] The resistors R1-R8 have the same resistance and function asvoltage dividing resistors that equally divides the potential differencebetween the high potential power supply VD and the low potential powersupply GND. Node N1 is defined between the high potential power supplyVD and the resistor R1. Nodes N2-N8 are defined between the resistorsR1-R8. Node N9 is defined between the resistor R8 and the low potentialpower supply GND. The potential differences between each node N1-N9 aresubstantially equal.

[0024] The first switch group 13 includes a plurality (e.g., eight) ofswitches SW1-SW8. The switches SW1-SW8 have the same ON resistance.Further, the switches SW1-SW8 each have a first terminal and a secondterminal. The first terminals of the switches SW1-SW8 are respectivelyconnected to nodes N2-N9. The second terminals of the switches SW1-SW8are connected to each other. In other words, the switches SW1-SW8 areconnected in parallel.

[0025] The second switch group 14 includes a plurality (e.g., eight) ofswitches SW9-SW16. The switches SW9-SW16 have the same ON resistance.Further, the switches SW9-SW16 each have a first terminal and a secondterminal. The first terminals of the switches SW9-SW16 are respectivelyconnected to nodes N1-N8. The second terminals of the switches SW9-SW16are connected to each other. In other words, the switches SW9-SW16 areconnected in parallel.

[0026] A preceding stage circuit 30 of the D/A converter circuit 11 isconnected to the second terminals of the second switch group 14. Asucceeding stage circuit 40 of the D/A converter circuit 11 is connectedto the second terminals of the first switch group 13. The D/A convertercircuit 11 outputs an analog signal OUT1, which is output from anactivated one of the switches SW1-SW8 and provided to the succeedingstage circuit 40.

[0027] A decoder circuit 15 (control circuit) provides control signalsto the switches SW1-SW8 of the first switch group 13 and the switchesSW9-SW16 of the second switch group 14 to activate and inactivate theswitches SW1-SW8, SW9-SW16.

[0028] The decoder circuit 15 receives a digital signal Din having aplurality of bits (in the preferred embodiment, three bits) . Thedecoder circuit 15 generates control signals, which activate andinactivate the switches SW1-SW8 and SW9-SW16, based on the digitalsignal Din.

[0029]FIG. 3 is a table illustrating the control logic of the D/Aconverter circuit 11 used by the decoder circuit 15. The decoder circuit15 generates first and second control signals S1, S2 based on the threebit digital signal Din to activate one of the switches SW1-SW8 and oneof the switches SW9-SW16. In this state, the decoder circuit 15generates the first and second control signals S1, S2 to simultaneouslyactivate one switch in each of the switch groups 13, 14. The activatedswitches are determined so that the absolute value of the voltagedifference between the node connected to the activated switch of thefirst switch group 13 and the high potential power supply VD issubstantially equal to the absolute value of the voltage differencebetween the node connected to the activated switch of the second switchgroup 14 and the low potential power supply GND.

[0030] For example, the decoder circuit 15 generates the first andsecond control signals S1, S2 so that the switch SW1 of the first switchgroup 13 and the switch SW16 of the second switch group 14 aresimultaneously activated. In this state, the absolute value of thevoltage difference (first voltage difference absolute value) betweennode N2, which is connected to the activated switch SW1, and the highpotential power supply VD is about the same as the absolute value of thevoltage difference (second voltage difference absolute value) betweennode N8, which is connected to the activated switch SW16, and the lowpotential power supply GND.

[0031] The decoder circuit 15 generates the first control signal S1based on a digital signal Din of, for example, “000” to activate theswitch SW1 and deactivate the other switches SW2-SW8 in the first switchgroup 13. Further, the decoder circuit 15 generates the second controlsignal S2 to activate the switch SW16 and deactivate the other switchesSW9-SW15 in the second switch group 14. As a result, the voltagedividing circuit 12 generates an analog signal OUT1 having the dividedvoltage at N2, which is 7/8×VD, via the activated switch SW1. Referringto FIG. 3, the decoder circuit 15 simultaneously activates one of theswitches SW1-SW8 and one of the switches SW9-SW16 based on the digitalsignal Din. In this manner, the voltage dividing circuit 12 outputs thedivided voltage at the node associated with the activated one of theswitches SW1-SW8. In other words, the voltage dividing circuit 12outputs one of the divided voltages of 0/8×VD to 7/8×VD at nodes N2-N9via the activated one of the switches SW1-SW8.

[0032] The operating principle of the D/A converter circuit 11 will nowbe described with reference to FIG. 4. FIG. 4 shows a D/A convertercircuit 21, which is used to illustrate the principle of the D/Aconverter circuit 11 of FIG. 2. The D/A converter circuit 21 includes avoltage dividing circuit 22 connected between a high potential powersupply VD and a low potential power supply GND. In the D/A convertercircuit 21, the voltage at the high potential power supply VD is 3.0V(volts) and the voltage of the low potential power supply GND is 0.0V(volts).

[0033] The voltage dividing circuit 22 includes resistors R21-R26connected in series between the high potential power supply VD and thelow potential power supply GND. The resistors R21-R26 have the sameresistance. In other words, each resistor R21-R26 functions as a voltagedividing resistor that equally divides the potential difference betweenthe high potential power supply VD and the low potential power supplyGND. Accordingly, at nodes N21-N25 between the resistors R21-R26, thepotential difference between the high potential power supply VD and nodeN21, the potential differences between adjacent nodes N21-N25, and thepotential difference between node N25 and the low potential power supplyGND are about the same.

[0034] Each node N21-N25 is connected to first terminals of switches,which form a first switch group. The switches of the first switch grouphave second terminals, which are connected to one another. In the samemanner, each node N21-N25 is connected to second terminals of switches,which form a second switch group. The switches of the second switchgroup have first terminals, which are connected to one another. FIG. 4shows only switches SW21, SW22 of the first switch group and switchesSW23, SW24 of the second switch group. The switches SW21, SW22, SW23,and SW24 are respectively connected to nodes N21, N22, N25, and N24. InFIG. 4, a first capacitor C1 includes the capacitance of each switch inthe first switch group and the capacitance of a succeeding stage circuit(not shown) that is connected to node N26. A second capacitor C2includes the capacitance of each switch in the second switch group andthe capacitance of a preceding stage circuit (not shown) that isconnected to node N27.

[0035] A decoder circuit (not shown) generates control signals based ona digital signal to simultaneously activate one of the switches in thefirst switch group and one of the switches in the second switch group.That is, the decoder circuit generates a first control signal and asecond control signal to activate and inactivate each switch of thefirst and second switch groups based on the digital signal. Morespecifically, the decoder circuit generates the first and second controlsignals to simultaneously activate one switch in each of the switchgroups. The activated switches are determined so that the absolute valueof the voltage difference between the node connected to the activatedswitch of the first switch group and the high potential power supply VDis substantially equal to the absolute value of the voltage differencebetween the node connected to the activated switch of the second switchgroup and the low potential power supply.

[0036] The D/A converter circuit 21 outputs an analog signal OUT2 havingthe divided voltage at the node connected to the activated switch of thefirst switch group.

[0037] For example, if the switch SW21 of the first switch group and theswitch SW23 of the second switch group are activated, the dividedvoltage at node N21 (5/6×VD=2.5V) is applied to node N26 via theactivated switch SW21, as shown in FIG. 5(a). In other words, an analogsignal OUT2 having divided voltage 2.5V is output from node N26. Thischarges the first capacitor C1 to 2.5V.

[0038] Further, referring to FIG. 5(a), the activated switch SW23applies the divided voltage at node N25 (1/6×VD=0.5V) to node N27. Thischarges the second capacitor C2 to 0.5V.

[0039] Then, at time t1, the switches SW22, SW24 are activated and theswitches SW21, SW23 are inactivated. This switches the node connected tothe first capacitor C1 from N21 to N22, while the first capacitor C1remains charged at 2.5V. The divided voltage at node N22 (4/6×VD=2.0V)is lower than the divided voltage at node N21 (2.5V). Accordingly,voltage that is higher than the divided voltage (2.0V) is applied tonode N22, as shown in FIG. 5(b). That is, in the first capacitor C1, acharge of 0.5V becomes excessive immediately after the switching theactivated switches.

[0040] Further, the activation of the switches SW22, SW24 and theinactivation of the switches SW21, SW23 switches the node connected tothe second capacitor C2 from N25 to N24, while the second capacitor C2remains charged at 0.5V. The divided voltage at node N24 (2/6×VD=1.0V)is higher than the divided voltage at node N25 (0.5V). Accordingly,referring to FIG. 5(b), voltage lower than the divided voltage (1.0V) isapplied to node N24. That is, in the second capacitor C2, a charge of0.5V becomes deficient immediately after switching the activatedswitches.

[0041] The excess charge of 0.5V in the first capacitor C1 is dischargedfrom the second capacitor C2 through the switch SW22, the resistors R23,R24, and the switch SW24. That is, the excess charge of the firstcapacitor C is transferred to compensate for the deficient charge of thesecond capacitor C2. This decreases the potential at node N22, as shownin FIG. 5(b), and the potential at node N26 is stabilized at the samepotential as that at node N22. Further, the potential at node N24increases, and the potential at node N27 is stabilized at the samepotential as that at node N24.

[0042] As shown in FIG. 5(a), the potential at node N26 stabilizes ataround time t3. That is, the time required for voltage conversion byswitching switches is the time spanning from time t1, at which theactivated switches are switched, to time t3, at which the potential atnode N26 stabilizes.

[0043] Referring to FIGS. 5(a) and 5(b), the broken lines show thewaveforms of the output voltage at nodes N32, N36 in the prior art D/Aconverter circuit 31 of FIG. 1 when the voltage of the high potentialpower supply VD is 3.0V and the voltage of the low potential powersupply GND is 0.0V.

[0044] When the switch SW31 is activated in the prior art D/A convertercircuit 31, a divided voltage of 2.5V is generated at node N31. If theswitch SW31 is inactivated from this state at time t1, the excess chargeof the capacitor C3 applies to node N32 a voltage that is higher thanthe divided voltage (2.0V) at node N32, as shown by the broken line inFIG. 5(b). The switching of the activated switches SW31, SW32 dischargesthe excess charge of the capacitor C3 to the low potential power supplyGND via the switch SW32 and the four resistors R33-R36.

[0045] In this state, as shown by the broken line in FIG. 5(a), thepotential at node N36 stabilizes at around time t4. That is, the timerequired for voltage conversion by switching the switches SW31, SW32 isthe time spanning from time t1, at which the activated switches areswitched, to time t4, at which the potential at node N36 stabilizes.

[0046] Referring to FIG. 4, in the preferred embodiment, the firstswitch group includes the switches SW21, SW22 and the second switchgroup includes the switches SW23, SW24. This structure discharges theexcess charge of the first capacitor C1 to the second capacitor C2through a route having a small resistance (e.g., the resistances R23,R24) and reduces the discharge time. Accordingly, the voltage conversiontime when switching the activated switches is reduced, as shown in FIG.5(a).

[0047] The D/A converter circuit 11 of FIG. 2 has a first capacitance(corresponding to the first capacitor C1 of FIG. 4), which includes thecapacitance of the elements in the first switch group 13 and thecapacitance of the succeeding stage circuit 40 of the D/A convertercircuit 11. Further, the D/A converter circuit 11 has a secondcapacitance (corresponding to the second capacitor C2 of FIG. 4), whichincludes the capacitance of the elements in the second switch group 14and the capacitance of a preceding stage circuit 30 of the D/A convertercircuit 11.

[0048] In the D/A converter circuit 11 of FIG. 2, a capacitorcorresponding to the first capacitance may be connected to the secondterminals of the switches SW1-SW8 of the first switch group 13. Further,a capacitor corresponding to the second capacitance may be connected tothe second terminals of the switches SW9-SW16 of the second switch group14.

[0049] When the activated switches in the first switch group 13 and thesecond switch group 14 are switched based on the decoder circuit controllogic of FIG. 3, the charging or discharging of the first capacitor,which is excess or deficient in charge, is performed through a routeformed by the resistors R1-R8 that produce a small resistance.

[0050] When the switch SW1 of the first switch group 13 is activated andthe switch SW16 of the second switch group 14 is activated, and then theswitches SW1, SW16 are deactivated and the switches SW2, SW15 areactivated, the excess charge of the first capacitor is discharged to thesecond capacitor through the four resistors R3-R6.

[0051] For example, if the switches SW1, SW16 are activated, and theswitches SW4, SW13 are activated afterward, the excess charge of thefirst capacitor is discharged to the second capacitor without passingthrough a resistor. In other words, the time for discharge from thefirst capacitor to the second capacitor is shortest when the switchesSW4, SW13, which are connected to node N5, are simultaneously activatedin such manner. Accordingly, in this case, the voltage conversion timeis shortest.

[0052] The voltage conversion time is shortened in the same manner whenthe second capacitor charges the first capacitor.

[0053] For example, if the switches SW8, SW9 are first activated, andthe switches SW4, SW13 are then activated, the deficient charge of thefirst capacitor is compensated for directly by the second capacitorwithout a resistor. That is, the time for charging the first capacitorwith the second capacitor is shortest. Accordingly, in this case, thevoltage conversion time is shortest.

[0054] The D/A converter circuit 11 of the preferred embodiment has theadvantages discussed below.

[0055] (1) The voltage dividing circuit 12 includes the resistors R1-R8,which have the same resistance, the first switch group 13, and thesecond switch group 14. The resistors R1-R8 are connected in seriesbetween the high potential power supply VD and the low potential powersupply GND to equally divide the potential difference between the highpotential power supply VD and the low potential power supply GND. Basedon the digital signal Din, the decoder circuit 15 activates one of theswitches SW1-SW8 in the first switch group 13 and one of the switchesSW9-SW16 in the second switch group 14. The activated switches aredetermined so that the absolute value of a first voltage differencebetween the node connected to the activated switch of the first switchgroup 13 and the high potential power supply VD is substantially equalto the absolute value of a second voltage difference between the nodeconnected to the activated switch of the second switch group 14 and thelow potential power supply GND. Accordingly, when switching theactivated switches, a first capacitor, which includes the elementcapacitance of the first switch group 13 and the capacitance of asucceeding stage circuit of the D/A converter circuit 11, is charged ordischarged through a route having a small resistance. This reduces thevoltage conversion time of the analog signal OUT1.

[0056] (2) At one of nodes N2-N8, the connected one of the switchesSW1-SW8 of the first switch group 13 and the connected one of theswitches SW9-SW16 are simultaneously activated. Accordingly, the timefor converting voltage is reduced regardless of the resistance of theresistors R1-R8. This reduces the voltage conversion time withoutincreasing the current consumption between the high potential powersupply VD and the low potential power supply GND.

[0057] It should be apparent to those skilled in the art that thepresent invention may be embodied in many other specific forms withoutdeparting from the spirit or scope of the invention. Particularly, itshould be understood that the present invention may be embodied in thefollowing forms.

[0058] The number of the resistors R1-R8 and the switches SW1-SW8,SW9-SW16 may be changed as required.

[0059] The number of bits in the digital signal Din may be changed asrequired.

[0060] A low potential power supply having a power supply voltage lowerthan that of the high potential power supply may be used in lieu of theground GND.

[0061] A third switch group formed by a plurality of switchesrespectively connected to nodes N1-N9 may be provided.

[0062] The voltage dividing circuit 12, which includes the two switchgroups 13, 14, may be connected in series to another voltage dividingcircuit to provide four or more switch groups.

[0063] The absolute value of the first voltage difference between theactivated switch of the first switch group 13 and the high potentialpower supply VD and the absolute value of the second voltage differencebetween the activated switch of the second switch group 14 and the lowpotential power supply GND do not necessarily have to be the same. Theswitches of the first and second switch groups 13, 14 arrangedsymmetrically relative to a predetermined node (or resistor) may beactivated or deactivated. For example, in the D/A converter circuit 11of FIG. 2, the switch SW2 and the switch SW11 may be simultaneouslyactivated. In this case, the voltage conversion time when the switchesSW2, SW11 are activated is shortest.

[0064] The present examples and embodiments are to be considered asillustrative and not restrictive, and the invention is not to be limitedto the details given herein, but may be modified within the scope andequivalence of the appended claims.

What is claimed is:
 1. A D/A converter circuit comprising: a pluralityof impedance elements connected in series between a first power supplyand a second power supply; a plurality of switch groups including afirst switch group and a second switch group, wherein the first switchgroup is formed by a plurality of first switches connected to at least aplurality of nodes between the plurality of impedance elements, and thesecond switch group is formed by a plurality of second switchesconnected to at least the plurality of nodes; and a control circuitconnected to the switch groups for selectively closing one of the firstswitches and one of the second switches.
 2. The D/A converter circuitaccording to claim 1, wherein the control circuit selectively closes theone of the first switches and the one of the second switches that aresymmetrically arranged relative to a predetermined one of the pluralityof nodes.
 3. The D/A converter circuit according to claim 1, wherein thecontrol circuit selectively closes the one of the first switches and theone of the second switches that are symmetrically arranged relative to apredetermined one of the plurality of impedance elements.
 4. The D/Aconverter circuit according to claim 1, wherein the control circuitsimultaneously closes the one of the first switches and the one of thesecond switches.
 5. The D/A converter circuit according to claim 1,wherein a first node voltage is generated at a first node connected tothe closed one of the first switches, and a second node voltage isgenerated at a second node connected to the closed one of the secondswitches, the control circuit closing the one of the first switches andthe one of the second switches so that an absolute value of a firstvoltage difference between the first node voltage and the voltage of thefirst power supply is substantially the same as an absolute value of asecond voltage difference between the second node voltage and thevoltage of the second power supply.
 6. The D/A converter circuitaccording to claim 1, wherein the number of the first switches and thenumber of the second switches are the same, and the first and secondswitches each have the same ON resistance.
 7. The D/A converter circuitaccording to claim 1, wherein the impedance elements each have the sameimpedance.
 8. The D/A converter circuit according to claim 1, whereinthe first power supply is a high potential power supply and the secondpower supply is a low potential power supply.
 9. A D/A converter circuitcomprising: a plurality of resistors connected in series between a firstpower supply and a second power supply, wherein the plurality ofresistors include a first resistor adjacent to the first power supplyand a second resistor adjacent to the second power supply; a firstswitch group formed by a plurality of first switches connected to aplurality of inter-resistor nodes between the resistors; a second switchgroup formed by a plurality of second switches connected to theinter-resistor nodes; and a decoder circuit connected to the first andsecond switch groups for selectively closing one of the first switchesand one of the second switches.
 10. The D/A converter circuit accordingto claim 9, wherein one of the plurality of first switches is connectedto a first inter-power source node between the first power supply andthe first resistor, and one of the plurality of second switches isconnected to a second inter-power source node between the second powersource and the second resistor.
 11. The D/A converter circuit accordingto claim 9, wherein the decoder circuit selectively closes the one ofthe first switches and the one of the second switches that aresymmetrically arranged relative to a predetermined one of the pluralityof inter-resistor nodes.
 12. The D/A converter circuit according toclaim 9, wherein the decoder circuit selectively closes the one of thefirst switches and the one of the second switches that are symmetricallyarranged relative to a predetermined one of the plurality of resistors.13. The D/A converter circuit according to claim 9, wherein a first nodevoltage is generated at a first inter-resistance node connected to theclosed one of the first switches, and a second node voltage is generatedat a second inter-resistance node connected to the closed one of thesecond switches, the decoder circuit closing the one of the firstswitches and the one of the second switches so that an absolute value ofa first voltage difference between the first node voltage and thevoltage of the first power supply and an absolute value of a secondvoltage difference between the second node voltage and the voltage ofthe second power supply are substantially the same.
 14. The D/Aconverter circuit according to claim 9, wherein the number of the firstswitches and the number of the second switches are the same, and thefirst and second switches each have the same ON resistance.
 15. The D/Aconverter circuit according to claim 9, wherein the impedance elementseach have the same impedance.
 16. The D/A converter circuit according toclaim 9, wherein the first power supply is a high potential power supplyand the second power supply is a low potential power supply.